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Freescale Semiconductor /MKV11Z7 /SIM /SOPT6

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Interpret as SOPT6

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTM3FLT0 0 (0)FTM4FLT0 0 (0)FTM5FLT0 0 (0)FTM3TRG0SRC 0 (0)FTM3TRG1SRC 0 (0)FTM3TRG2SRC 0 (0)FTM4TRG0SRC 0 (0)FTM4TRG1SRC 0 (0)FTM4TRG2SRC 0 (0)FTM5TRG0SRC 0 (0)FTM5TRG1SRC 0 (0)FTM5TRG2SRC 0 (00)FTM4CH0SRC 0 (00)FTM5CH0SRC 0 (00)FTM3CLKSEL 0 (00)FTM4CLKSEL 0 (00)FTM5CLKSEL

FTM4CLKSEL=00, FTM3FLT0=0, FTM5FLT0=0, FTM3TRG0SRC=0, FTM5CLKSEL=00, FTM3CLKSEL=00, FTM5TRG0SRC=0, FTM5CH0SRC=00, FTM4TRG1SRC=0, FTM3TRG2SRC=0, FTM4TRG0SRC=0, FTM5TRG2SRC=0, FTM3TRG1SRC=0, FTM4TRG2SRC=0, FTM4FLT0=0, FTM4CH0SRC=00, FTM5TRG1SRC=0

Description

Systems Option Register 6

Fields

FTM3FLT0

FTM3 Fault 0 Select

0 (0): FTM3_FLT0 pin

1 (1): CMP0 out
FTM4FLT0

FTM4 Fault 0 Select

0 (0): FTM4_FLT0 pin

1 (1): CMP0 out
FTM5FLT0

FTM5 Fault 0 Select

0 (0): FTM5_FLT0 pin

1 (1): CMP0 out
FTM3TRG0SRC

FlexTimer 3 Hardware Trigger 0 Source Select

0 (0): CMP0 output drives FTM3 hardware trigger 0

1 (1): FTM5 channel match drives FTM3 hardware trigger 0
FTM3TRG1SRC

FlexTimer 3 Hardware Trigger 1 Source Select

0 (0): PDB1 output drives FTM3 hardware trigger 1

1 (1): FTM4 channel match drives FTM3 hardware trigger 1
FTM3TRG2SRC

FlexTimer 3 Hardware Trigger 2 Source Select

0 (0): CMP0 output drives FTM3 hardware trigger 2

1 (1): CMP1 output drives FTM3 hardware trigger 2
FTM4TRG0SRC

FlexTimer 4 Hardware Trigger 0 Source Select

0 (0): CMP0 output drives FTM4 hardware trigger 0

1 (1): FTM3 channel match drives FTM4 hardware trigger 0
FTM4TRG1SRC

FlexTimer 4 Hardware Trigger 1 Source Select

0 (0): PDB1 output trigger 1 drives FTM4 hardware trigger 1

1 (1): FTM5 channel match drives FTM4 hardware trigger 1
FTM4TRG2SRC

FlexTimer 4 Hardware Trigger 2 Source Select

0 (0): CMP0 output drives FTM4 hardware trigger 2

1 (1): CMP1 output drives FTM4 hardware trigger 2
FTM5TRG0SRC

FlexTimer 5 Hardware Trigger 0 Source Select

0 (0): CMP0 output drives FTM5 hardware trigger 0

1 (1): FTM3 channel match drives FTM5 hardware trigger 0
FTM5TRG1SRC

FlexTimer 5 Hardware Trigger 1 Source Select

0 (0): PDB1 output trigger 1 drives FTM5 hardware trigger 1

1 (1): FTM4 channel match drives FTM5 hardware trigger 1
FTM5TRG2SRC

FlexTimer 5 Hardware Trigger 2 Source Select

0 (0): CMP0 output drives FTM5 hardware trigger 2

1 (1): CMP1 output drives FTM5 hardware trigger 2
FTM4CH0SRC

FTM4 channel 0 input capture source select

0 (00): FTM4_CH0 signal

1 (01): CMP0 output

2 (10): CMP1 output
FTM5CH0SRC

FTM5 channel 0 input capture source select

0 (00): FTM5_CH0 signal

1 (01): CMP0 output

2 (10): CMP1 output
FTM3CLKSEL

FTM3 External Clock Pin Select

0 (00): FTM3 external clock driven by FTM_CLKIN0 pin

1 (01): FTM3 external clock driven by FTM_CLKIN1 pin

2 (10): FTM3 external clock driven by FTM_CLKIN2 pin
FTM4CLKSEL

FTM4 External Clock Pin Select

0 (00): FTM4 external clock driven by FTM_CLKIN0 pin

1 (01): FTM4 external clock driven by FTM_CLKIN1 pin

2 (10): FTM4 external clock driven by FTM_CLKIN2 pin
FTM5CLKSEL

FTM5 External Clock Pin Select

0 (00): FTM5 external clock driven by FTM_CLKIN0 pin

1 (01): FTM5 external clock driven by FTM_CLKIN1 pin

2 (10): FTM5 external clock driven by FTM_CLKIN2 pin

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data